This invention relates to a dividing apparatus, and more particularly to a high-speed dividing apparatus for electronic digital computers.
A conventional basic binary dividing apparatus generates a quotient bit by bit while a divisor is added to or subtracted from a dividend or a partial remainder repeatedly in accordance with the non-restoring algorithm. There is an improved apparatus which is capable of generating a plurality of quotient bits in one cycle. This apparatus is designed to shift a partial remainder, add or subtract a suitable multiple of a divisor to or from the shifted partial remainder, and, based on the resultant partial remainder, estimate a plurality of quotient bits while determining the shift length of the partial remainder in preparation for the subsequent operation. However, the drawbacks of this apparatus reside in that it is difficult to reduce the cycle time since the shift length depends upon the result of each addition or subtraction.
Another improved apparatus of this kind which is designed with a view to eliminating these drawbacks is disclosed in Japanese Patent Publication No. 17188/1969. This improved apparatus is characterized in that two quotient bits can be obtained from the values of the upper three bits of both a partial remainder and a divisor with shift of a constant length. However, it requires the multiples by 0, 1/2, 3/4, 1, and 3/2 of a divisor, and the multiple by 3/2, among others, has to be prepared prior to starting a division. It is further necessary that normalization should be done before starting a division to shift a divisor until "1" appears in the MSB (Most Significant Bit) position, and also to shift a dividend by the same number of bits. Such various kinds of preparatory operations must be carried out prior to the starting of a division operation, so that much time is necessarily spent in carrying out various kinds of pre-processing steps in addition to the dividing operation itself. Moreover, a selector circuit which selects an appropriate multiple of a divisor in accordance with the values of a partial remainder and a divisor is required, which leads to an increase in the required amount of hardware.
Further, the above-described conventional dividing apparatuses utilize a full adder which is used for various kinds of computations other than division. Therefore, a plurality of selector circuits and various working registers are concerned in a dividing operation. Accordingly, the total operating time for carrying out a division cannot be reduced to the level theoretically estimated.